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- Shunichi Toida
- 3214 Engr and Comp Sciences Bldg
-
Norfolk,
VA
23529
- 757-683-3392
- stoida@odu.edu
-
Education
- University of Illinois,
1969
- Major: Electrical Engineering
- Degree: Ph. D.
- University of Illinois,
1966
- Major: Electrical Engineering
- Degree: M.S.
- University of Tokyo,
1959
- Major: Electrical Engineering
- Degree: B.S.
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Articles
- Toida, S., and Roa, N. S. (1994). On polynomial-time testable combinational circuits. IEEE Trans. on Computers, 23 (11), (pp. 1298-1308).
- Toida, S., Olariu, S., and Zubair, M. (1988). On the conjecture of Plaisted and Hong. Journal on Algorithms, 9 (4), (pp. 597-598).
- Toida, S. (1985). A decomposition of a graph into dense subgraphs. IEEE Trans. on Circuits and Systems, CAS-32 (6), (pp. 583-589).
- Toida, S. (1982). A graph model for fault diagnosis. Journal of Digital Systems, VI (4), (pp. 345-365).
- Toida, S., and Fujiwara, H. (1982). The complexity of fault detection problems for combinational logic circuits. IEEE Trans. on Computers, C-31 (6), (pp. 555-560).